1. Field of the Invention
The present application relates to a semiconductor memory and a semiconductor memory system having an error correction function.
2. Description of Related Art
Recently, semiconductor memories including an error correction circuit for remedying a defective bit is mounted are proposed. In these semiconductor memories, when a ratio DN/PN of the number of bits DN of data and the number of bits PN of an error correction code (parity code) is larger, a memory cell area for storing the parity code (parity memory cell) is relatively reduced, whereby area efficiency is improved. On the contrary, in general, when the ratio DN/PN is increased, a remedy efficiency, which is the ratio 1/(DN+PN) of the number of bits of data to be remedied to the total number of bits, is reduced. That is, improvement of the area efficiency is in contradiction to improvement of the remedy efficiency. Japanese Laid-open Patent Publication No. 2005-216437, for example, discloses a method of correcting a data error using a horizontal/vertical parity code to improve both the area efficiency and the remedy efficiency.
Additional advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become more apparent to those skilled in the art upon examination of the following or upon learning by practice of the invention.